A novel design has been proposed to safely apply the NCLSCR (NMOS-controlled lateral SCR) and PCLSCR (PMOS-controlled lateral SCR) devices for whole-chip ESD (electrostatic discharge) protection in CMOS IC's without causing the unexpected operation errors or the VDD-to-VSS latchup issue. By using the cascode configuration, the ESD protection circuit with the cascode NCLSCR's or PCLSCR's has a tunable holding voltage greater than VDD of the IC's. Such cascode NCLSCR's (or PCLSCR's) can provide the CMOS IC's with effective ESD protection but without accidentally triggering on by the overshooting (under-shooting) noise pulses in the system applications. This novel cascode NCLSCR's (PCLSCR's) design has been practically applied to protect the IC's in a 0.35-μm silicide CMOS technology with the HBM ESD robustness above 3KV.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 1 Jan 1998|
|Event||Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
Duration: 11 May 1998 → 14 May 1998