Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique

J. N. Burghartz; J. Wamock; J. D. Cressler; C. L. Stanis; R. C. McIntosh; J. Y.C. Sun; J. H. Comfort; J. M.C. Stork; K. A. Jenkins; E. F. Crabbé; W. Lee; M. Gilbert

Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique

J. N. Burghartz^*, J. Wamock, J. D. Cressler, C. L. Stanis, R. C. McIntosh, J. Y.C. Sun, J. H. Comfort, J. M.C. Stork, K. A. Jenkins, E. F. Crabbé, W. Lee, M. Gilbert

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-alined bipolar transistor structure.

Original language	English
Title of host publication	European Solid-State Device Research Conference
Editors	Herman E. Maes, Roger J. Van Overstraeten, Robert P. Mertens
Publisher	IEEE Computer Society
Pages	531-534
Number of pages	4
ISBN (Electronic)	0444894780
State	Published - 1992
Event	22nd European Solid State Device Research Conference, ESSDERC 1992 - Leuven, Belgium Duration: 14 Sep 1992 → 17 Sep 1992

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	22nd European Solid State Device Research Conference, ESSDERC 1992
Country	Belgium
City	Leuven
Period	14/09/92 → 17/09/92

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Burghartz, J. N., Wamock, J., Cressler, J. D., Stanis, C. L., McIntosh, R. C., Sun, J. Y. C., Comfort, J. H., Stork, J. M. C., Jenkins, K. A., Crabbé, E. F., Lee, W., & Gilbert, M. (1992). Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique. In H. E. Maes, R. J. Van Overstraeten, & R. P. Mertens (Eds.), European Solid-State Device Research Conference (pp. 531-534). [5435153] (European Solid-State Device Research Conference). IEEE Computer Society.

Burghartz, J. N. ; Wamock, J. ; Cressler, J. D. ; Stanis, C. L. ; McIntosh, R. C. ; Sun, J. Y.C. ; Comfort, J. H. ; Stork, J. M.C. ; Jenkins, K. A. ; Crabbé, E. F. ; Lee, W. ; Gilbert, M. / Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique. European Solid-State Device Research Conference. editor / Herman E. Maes ; Roger J. Van Overstraeten ; Robert P. Mertens. IEEE Computer Society, 1992. pp. 531-534 (European Solid-State Device Research Conference).

@inproceedings{d715d45172264ad6ad5b950ec55f8d6d,

title = "Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique",

abstract = "A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-alined bipolar transistor structure.",

author = "Burghartz, {J. N.} and J. Wamock and Cressler, {J. D.} and Stanis, {C. L.} and McIntosh, {R. C.} and Sun, {J. Y.C.} and Comfort, {J. H.} and Stork, {J. M.C.} and Jenkins, {K. A.} and Crabb{\'e}, {E. F.} and W. Lee and M. Gilbert",

year = "1992",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "531--534",

editor = "Maes, {Herman E.} and {Van Overstraeten}, {Roger J.} and Mertens, {Robert P.}",

booktitle = "European Solid-State Device Research Conference",

address = "United States",

note = "null ; Conference date: 14-09-1992 Through 17-09-1992",

}

Burghartz, JN, Wamock, J, Cressler, JD, Stanis, CL, McIntosh, RC, Sun, JYC, Comfort, JH, Stork, JMC, Jenkins, KA, Crabbé, EF, Lee, W & Gilbert, M 1992, Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique. in HE Maes, RJ Van Overstraeten & RP Mertens (eds), European Solid-State Device Research Conference., 5435153, European Solid-State Device Research Conference, IEEE Computer Society, pp. 531-534, 22nd European Solid State Device Research Conference, ESSDERC 1992, Leuven, Belgium, 14/09/92.

Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique. / Burghartz, J. N.; Wamock, J.; Cressler, J. D.; Stanis, C. L.; McIntosh, R. C.; Sun, J. Y.C.; Comfort, J. H.; Stork, J. M.C.; Jenkins, K. A.; Crabbé, E. F.; Lee, W.; Gilbert, M.

European Solid-State Device Research Conference. ed. / Herman E. Maes; Roger J. Van Overstraeten; Robert P. Mertens. IEEE Computer Society, 1992. p. 531-534 5435153 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique

AU - Burghartz, J. N.

AU - Wamock, J.

AU - Cressler, J. D.

AU - Stanis, C. L.

AU - McIntosh, R. C.

AU - Sun, J. Y.C.

AU - Comfort, J. H.

AU - Stork, J. M.C.

AU - Jenkins, K. A.

AU - Crabbé, E. F.

AU - Lee, W.

AU - Gilbert, M.

PY - 1992

Y1 - 1992

N2 - A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-alined bipolar transistor structure.

AB - A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-alined bipolar transistor structure.

UR - http://www.scopus.com/inward/record.url?scp=84926420060&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84926420060

T3 - European Solid-State Device Research Conference

SP - 531

EP - 534

BT - European Solid-State Device Research Conference

A2 - Maes, Herman E.

A2 - Van Overstraeten, Roger J.

A2 - Mertens, Robert P.

PB - IEEE Computer Society

Y2 - 14 September 1992 through 17 September 1992

ER -

Burghartz JN, Wamock J, Cressler JD, Stanis CL, McIntosh RC, Sun JYC et al. Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique. In Maes HE, Van Overstraeten RJ, Mertens RP, editors, European Solid-State Device Research Conference. IEEE Computer Society. 1992. p. 531-534. 5435153. (European Solid-State Device Research Conference).

Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique

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