Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique

J. N. Burghartz*, J. Warnock, J. D. Cressler, C. L. Stanis, R. C. McIntosh, J. Y.C. Sun, J. H. Comfort, J. M.C. Stork, K. A. Jenkins, E. F. Crabbé, W. Lee, M. Gilbert

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-aligned bipolar transistor structure.

Original languageEnglish
Pages (from-to)531-534
Number of pages4
JournalMicroelectronic Engineering
Volume19
Issue number1-4
DOIs
StatePublished - Sep 1992

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