Non-recursive switch ed-capacitor decimator and interpolator circuits

Chung-Yu Wu, Shou Yuan Huang, Tsai Chung Yu, Yie Yuan Shieu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Non-recursive switched-capacitor decimator and interpolator are developed and analyzed in this paper. Their circuit structures are simple and the design procedure is concise and direct. Moreover, they have the advantages of less clock phases, low sensitivities to component and power-supply variations, good noise performance, and large dynamic range. Two design examples are presented. The consistence of simulation and theoretical results proves the correctness and usefulness of the proposed circuits.

Original languageEnglish
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1215-1218
Number of pages4
ISBN (Electronic)0780305930
DOIs
StatePublished - 1 Jan 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: 10 May 199213 May 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period10/05/9213/05/92

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