No cache-coherence: A single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips

Shu Hsuan Chou*, Chien Chih Chen, Chi Neng Wen, Yi Chao Chan, Tien-Fu Chen, Chao Ching Wang, Jinn Shyan Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

Consistent with the trend towards the use of many cores in SOC and 3D Chip techniques, this paper proposes a "single-cycle ring" interconnection (SC-Ring) with ultra-low latency and minimal complexity. The proposed SC-Ring allows multiple single-cycle transactions in parallel. The main features of the circuit-switched design include a set of 3-ported circuitswitched routers (4∼16) and a performance/timing effective arbiter. The arbiter, called "BTPC", features single-cycle arbitration and routing-control by means of the novel Binary-Tree paths convergence and path-prediction mechanisms, to provide a highly reduced time complexity. By combining this with the integration of 3D chips, the proposed ring-based interconnection offers several advantages for hierarchical clustering in future many-core systems, in terms of cost, latency, and power reductions. Moreover, based on the proposed SC-Ring, this work realizes a "level-1 non-uniform cache architecture" (L1-NUCA) for fast data communication without cache-coherency in facilitating multithreading/multi-core as a case study. Finally, experimental results show that our approach yields promising performance.

Original languageEnglish
Title of host publication2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Pages587-592
Number of pages6
DOIs
StatePublished - 10 Nov 2009
Event2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States
Duration: 26 Jul 200931 Jul 2009

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference2009 46th ACM/IEEE Design Automation Conference, DAC 2009
CountryUnited States
CitySan Francisco, CA
Period26/07/0931/07/09

Keywords

  • Arbitration
  • Level-1 non-uniform cache architecture
  • Memory structure
  • Multi-core
  • NOC
  • Ring interconnection
  • SOC
  • Single-cycle transactions

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