Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs

Chuan Hui Shen, Wei Yen Chen, Shen Yang Lee, Po Yi Kuo, Tien Sheng Chao*

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

In this article, poly-Si gate-all-around (GAA) field effect transistors (FETs) using sidewall damascene method are successfully demonstrated. By manipulating the stress which is imposed by nitride layer, the crystallinity of poly-Si channels can be modified easily by changing the thickness of nitride layer. The better crystallinity of the devices with 60 nm top nitride is attributed to larger average grain size and fewer defects, leading to higher field-effect carrier mobility compared to 40 and 80 nm top nitride layer devices. Both n-type and p-type devices exhibit superior electrical characteristics including higher on-state current of 40 μA/μm (n-type) and 26 μA/μm (p-type), steep subthreshold swing of 82 mV/dec. (n-type) and 104 mV/dec. (p-type), an extremely low drain-induced barrier lowering (DIBL) of 4.6 mV/V (n-type) and 16.6 mV/V (p-type), and high Ion/Ioff current ratio larger than seven orders of magnitude. The thermal stability and gate stress reliability measurement of sidewall damascene GAA nanowire poly-Si devices were also investigated. With better crystallinity, electrical characteristics of GAA nanowire poly-Si devices degrade less under same elevated temperature condition. Devices characteristics remain unchanged after long gate stress time. This simple fabrication process makes it a potential candidate for future three-dimensional integrated-circuit (3D-IC) and low-cost Internet of Things (IoTs) applications.

Original languageEnglish
Article number9044627
Pages (from-to)322-327
Number of pages6
JournalIEEE Transactions on Nanotechnology
Volume19
DOIs
StatePublished - 1 Jan 2020

Keywords

  • Crystallinity
  • gate-all-around
  • poly-Si
  • stress
  • thermal reliability

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