NiSi salicide technology for scaled CMOS

Hiroshi Iwai*, Tatsuya Ohguro, Shun ichiro Ohmi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

282 Scopus citations


Salicide is one of the indispensable techniques for high-performance logic devices and its importance increases as the device dimensions become small towards sub-100 nm and hence, the source/drain sheet resistance becomes large. TiSi2 used popularly as the silicide material has been eventually replaced by CoSi2, because of its relatively stable nature during the salicide process. For sub-100-nm technology node, CoSi2 is expected to be further replaced by NiSi. NiSi has several advantages over TiSi2 and CoSi2 for the ultra-small CMOS process. They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance, (6) smaller contact resistance for both n- and p-Si, and (7) higher activation rate of B for SiGe poly gate electrode. In this paper, NiSi salicide technology is explained.

Original languageEnglish
Pages (from-to)157-169
Number of pages13
JournalMicroelectronic Engineering
Issue number1-2
StatePublished - Jan 2002
EventMaterials for Advanced Metallization (MAM 2001) - Sigtuna, Sweden
Duration: 5 Mar 20017 Mar 2001


  • Junction
  • Nickel
  • Resistance
  • Salicide
  • Silicide

Fingerprint Dive into the research topics of 'NiSi salicide technology for scaled CMOS'. Together they form a unique fingerprint.

Cite this