New VLSI architecture without global broadcast for 2-D digital filters

Lan-Da Van*, Chih Chun Tang, Shing Tenqchen, Wu Shiung Feng

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
DOIs
StatePublished - 1 Jan 2000
EventProceedings of the IEEE 2000 International Symposium on Circuits and Systems - Geneva, Switz
Duration: 28 May 200031 May 2000

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