A structure is proposed that makes it possible to shrink cell size without scaling of device dimensions. The NAND structure cell realizes a cell as small as 6. 43 mu m**2 using a 1. 0- mu m design rule. As a result, cell area per bit can be reduced by 30% compared with that of a 4-Mb EPROM using the conventional structure and the same design rule. It is found that each bit in a NAND cell is able to be programmed selectively. This high-performance NAND-structure cell is applicable to high-density nonvolatile memories as large as 8 Mb.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 1987|