New true-single-phase-clocking (TSPC) BiCMOS dynamic pipelined logic

Yuh Kuang Tseng*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

New true-single-phase-clocking BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. The circuit performance of the new BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits are simulated by using HSPICE in 1μm BiCMOS technology. Simulation results have shown that the operating frequency of the pipelined system which is constructed by the new dynamic latch logic circuits, is 204.1 MHz under 1.5 pF output loading at 2.3 V. It is 2.86 times of the operating frequency in the CMOS TSPC dynamic pipelined system.

Original languageEnglish
Pages (from-to)49-52
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 1 Jan 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: 31 May 19983 Jun 1998

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