New sub-20nm transistors - Why and how

Chen-Ming Hu*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Two new MOSFET structures are candidates for sub-20nm IC technologies according to International Technology Roadmap for Semiconductors. FinFET and UTB-SOI transistors are poised to replace today's MOSFETs and will provide much needed relief to ICs from their power and device variation predicaments.

Original languageEnglish
Title of host publication2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
Pages460-463
Number of pages4
StatePublished - 16 Sep 2011
Event2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 - San Diego, CA, United States
Duration: 5 Jun 20119 Jun 2011

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
CountryUnited States
CitySan Diego, CA
Period5/06/119/06/11

Keywords

  • ETSOI
  • FDSOI
  • FinFET
  • Low-power
  • MOSFET
  • non-planar
  • Scaling
  • Transistor
  • Tri-gate
  • UTB-SOI

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  • Cite this

    Hu, C-M. (2011). New sub-20nm transistors - Why and how. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 (pp. 460-463). [5981967] (Proceedings - Design Automation Conference).