A new large-signal equivalent circuit with input and output current signals for a nonsaturated bipolar junction transistor has been developed. Based upon this equivalent circuit, physical timing models of direct-coupled transistor logic (DCTL) and nonthreshold logic (NTL) have been derived through a general modeling methodology. It is shown from extensive comparisons with SPICE simulation results that the models have a maximum error of 25% in single-stage delay calculation and 10% in multi-stage delay calculation. Experimental results on NTL ring oscillators also partly substantiate the developed current-domain large-signal equivalent circuit and physical timing models. Good accuracy, wide applicable ranges of device/circuit parameters and input waveforms, and less CPU time and memory consumption than full transient simulations make the physical timing models feasible in optimization and CAD of high-speed bipolar ICs.