New NAND cell for ultra high density 5v-only EEPROMs.

Shirota Riichiro*, Y. Itoh, R. Nakayama, M. Momodomi, S. Inoue, R. Kirisawa, Y. Iwata, M. Chiba, F. Masuoka

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

10 Scopus citations


The NAND cell can be programmed and erased by a single 5-V supply and has an area that is 60% that of the current cell. Using the 1-μm design rule, the cell area per bit of the NAND cell and the current cell are 9.3 μm2 and 22 μm2, respectively. The NAND cell achieves high reliability and write and erase endurance exceeding 105 cycles. It is applicable to EEPROMs beyond 4 M bits.

Original languageEnglish
Pages (from-to)33-34
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 1 Dec 1988

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