The NAND cell can be programmed and erased by a single 5-V supply and has an area that is 60% that of the current cell. Using the 1-μm design rule, the cell area per bit of the NAND cell and the current cell are 9.3 μm2 and 22 μm2, respectively. The NAND cell achieves high reliability and write and erase endurance exceeding 105 cycles. It is applicable to EEPROMs beyond 4 M bits.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|State||Published - 1 Dec 1988|