New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area

Ming-Dou Ker*, Tung Yang Chen, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

Original languageEnglish
Pages103-108
Number of pages6
DOIs
StatePublished - 1 Dec 1997
EventProceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore
Duration: 21 Jul 199725 Jul 1997

Conference

ConferenceProceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA
CitySingapore, Singapore
Period21/07/9725/07/97

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