New layout arrangement to improve ESD robustness of large-array high-voltage nLDMOS

Wen Yi Chen*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

26 Scopus citations

Abstract

In high-voltage applications, large-array n-channel lateral DMOS (LA-nLDMOS) is usually required to provide high driving capability. However, without following the foundry-suggested electrostatic discharge (ESD) design guidelines in order to reduce total layout area, LA-nLDMOS is easily damaged once the parasitic bipolar junction transistor is triggered under ESD stresses. Accordingly, the bipolar triggering of LA-nLDMOS usually limits the ESD robustness of LA-nLDMOS, particularly in the open-drain structure. In this letter, a new layout arrangement for LA-nLDMOS has been proposed to suppress the bipolar triggering under ESD stresses. Measurement results in a 0.5-μm 16-V bipolar CMOS DMOS process have confirmed that the new proposed layout arrangement can successfully increase the human-body-model ESD level of the LA-nLDMOS with effective width of 3000 μm from the original 0.75 kV up to 2.75 kV.

Original languageEnglish
Article number5357417
Pages (from-to)159-161
Number of pages3
JournalIEEE Electron Device Letters
Volume31
Issue number2
DOIs
StatePublished - 1 Feb 2010

Keywords

  • Electrostatic discharge (ESD)
  • Lateral DMOS (LDMOS)
  • Open drain

Fingerprint Dive into the research topics of 'New layout arrangement to improve ESD robustness of large-array high-voltage nLDMOS'. Together they form a unique fingerprint.

Cite this