A sizing methodology called the near-characteristic waveform-synthesising method (NCWSM) is proposed to determine the device sizes of CMOS combinational logic circuits under a fixed delay specification. By using accurate physical timing models and the NCWSM, a fixed-delay sizing algorithm is developed and implemented, which sizes circuits quickly and globally. It can handle CMOS inverters, multi-input NAND/NOR gates, and AOI/OAI gates, all with device channel lengths down to 1.5 μm. It is shown through experimental verifications that the proposed algorithm can size a circuit with much smaller CPU time than that for the heuristic approach, and the resultant circuit power dissipations are nearly the same. As the circuit complexity increases, the above advantageous feature becomes more significant and the minimum realisable delay is even smaller than that of the heuristic approach. With high efficiency and delay accuracy, the proposed sizing algorithm and methodology can handle large-scale circuits with less design time. It can also serve to provide a good initial guess for more advanced sizing operations.
|Number of pages||8|
|Journal||IEE Proceedings E: Computers and Digital Techniques|
|State||Published - 1 Sep 1992|