New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's

Ming-Dou Ker*, Wen Yu Lo, Chung-Yu Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

A new experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of bulk CMOS IC's. The layout rules are extracted from the experimental testchips with the latchup sensors and different drawing spacings. A new latchup prevention design with additional internal guard rings between the I/O cells and the internal circuits is first investigated in the fabricated experimental testchips. Through detailed experimental verification including temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS IC's but still with enough latchup immunity in a 0.5-μm bulk CMOS technology.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherIEEE
Pages143-146
Number of pages4
ISBN (Print)0780354443
DOIs
StatePublished - 1 Jan 1999
EventProceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 - San Diego, CA, USA
Duration: 16 May 199919 May 1999

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceProceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99
CitySan Diego, CA, USA
Period16/05/9919/05/99

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  • Cite this

    Ker, M-D., Lo, W. Y., & Wu, C-Y. (1999). New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's. In Proceedings of the Custom Integrated Circuits Conference (pp. 143-146). (Proceedings of the Custom Integrated Circuits Conference). IEEE. https://doi.org/10.1109/CICC.1999.777261