A dry recess technology that is compatible with a self-aligned enhancement/depletion (E/D) MESFET IC process on 3-in GaAs wafers for gate lengths 1 mu m and below is presented. A self-limiting gate recess process called SLICE is used to maintain voltage threshold control and across-wafer uniformity of E-MESFETs. Using the dry gate recess E-MESFET, the authors have successfully fabricated state-of-the-art high transconductance E-MESFETs, E/D ring oscillators and E/D DCFL (direct coupled FET logic) dividers.
|Number of pages||4|
|State||Published - 1 Dec 1985|