New digit-serial three-operand multiplier over binary extension fields for highperformance applications

Chiou Yng Lee, Chia Chen Fan, Shyan-Ming Yuan, C. Y. Lee, C. C. Fan, S. M. Yuan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Digit-serial polynomial basis multipliers over GF(2m) are broadly applied in elliptic curve cryptography, because squaring and polynomial reduction in GF(2m) are simple operations. In this paper, we define a partial product formula to derive a new digit-serial three-operand multiplication algorithm. On the basis of the proposed algorithm, we have derived a new digit-serial structures for computing three-operand multiplication. Our proposed structures can reduce latency (clock cycles) by approximately 50% compared to the existing digitserial two-operand multipliers used to perform three-operand multiplication. Therefore, the proposed structure can achieve high-throughput designs. According to the analysis reports, the advantages of the proposed designs are a short critical path, a low area-delay product, and a high throughput.

Original languageEnglish
Title of host publication2017 2nd IEEE International Conference on Computational Intelligence and Applications, ICCIA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages498-502
Number of pages5
ISBN (Electronic)9781538620304
DOIs
StatePublished - 4 Dec 2017
Event2nd IEEE International Conference on Computational Intelligence and Applications, ICCIA 2017 - Beijing, China
Duration: 8 Sep 201711 Sep 2017

Publication series

Name2017 2nd IEEE International Conference on Computational Intelligence and Applications, ICCIA 2017
Volume2017-January

Conference

Conference2nd IEEE International Conference on Computational Intelligence and Applications, ICCIA 2017
CountryChina
CityBeijing
Period8/09/1711/09/17

Keywords

  • Binary extension fields
  • Digit-serial multiplier
  • Three-operand multiplication

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    Lee, C. Y., Fan, C. C., Yuan, S-M., Lee, C. Y., Fan, C. C., & Yuan, S. M. (2017). New digit-serial three-operand multiplier over binary extension fields for highperformance applications. In 2017 2nd IEEE International Conference on Computational Intelligence and Applications, ICCIA 2017 (pp. 498-502). (2017 2nd IEEE International Conference on Computational Intelligence and Applications, ICCIA 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CIAPP.2017.8167267