New developments in Schottky source/drain high-k/metal gate CMOS transistors

Ming Fu Li*, Sungjoo Lee, Shiyang Zhu, Rui Li, Jingde Chen, Albert Chin, D. L. Kwong

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review


Recent developments in Schottky source/drain high-k/metal gate CMOS transistors (SSDT) will be presented. Bulk SSDTs with 1.5-2 nm HfO2 (or HfAlO) gate dielectric and HfN/TaN metal gate have been fabricated using a novel low temperature process. The Si N-SSDT using YbSi2-x suicide, due to the lower Schottky electron barrier of YbSi2.x/Si, has demonstrated a record high Ion/Ioff ratio of ∼10 7 and a steep subthreshold slope of 75 mV/dec. For P-SSDT, the Si SSDT using PtSi silicide S/D shows excellent Ion/Ioff of ∼ 107-108 and subthreshold slope of ∼ 66 mV/dec, while the Ge SSDT using NiGe S/D shows Ion ∼ 5 times larger than that of the Si counterpart with PtSi S/D, due to the lower hole Schottky barrier and the higher hole mobility of Ge channel. The implant-free low temperature process relaxes the thermal budget of high-k dielectric and metal gate Fermi pinning. More improved performances are expected by using ultra-thin-body (UTB) SOI or GOI structures, showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.

Original languageEnglish
Number of pages2
StatePublished - 1 Dec 2005
Event207th ECS Meeting - Quebec, Canada
Duration: 16 May 200520 May 2005


Conference207th ECS Meeting

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