New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

Chih Ting Yeh*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 25 Jul 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

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