New design of 2 × VDD-tolerant power-rail ESD clamp circuit for mixed-voltage I/O buffers in 65-nm CMOS technology

Chih Ting Yeh*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

A new 2 × VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 × VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit. The proposed design with an SCR width of 50 μm can achieve a 6.5-kV human-body-model ESD level, a 300-V machine-model ESD level, and a low standby leakage current of only 103.7 nA at room temperature under the normal circuit operating condition with 1.8 V bias.

Original languageEnglish
Article number6153054
Pages (from-to)178-182
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number3
DOIs
StatePublished - 1 Mar 2012

Keywords

  • Electrostatic discharge (ESD)
  • holding voltage
  • mixed-voltage I/O buffers
  • power-rail ESD clamp circuit

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