In this paper, a new structure is proposed to implement the programmable gain controller with a wide dynamic range. The timing-duty controlled structure determines the attenuation values by changing the ratio of integration time between desired attenuation value and unity gain instead of the resistors or capacitors ratios. It reduces the chip area by applying the timing-duty controlled concept on the switched-capacitor(SC) circuits. But in the original timing-duty controlled circuit, the system clock frequency would be too high to be implemented in order to have a high resolution. A new timing-duty controlled programmable gain controller(TDGC) is proposed and reduces the required system clock frequency by one-third and one-fourth successfully. The advantages of this new structure have two: one is absent of the selectable capacitor array, thus it takes less chip area than ordinary SC circuits. The other is that the TDGC circuit is used more efficient by modifying the timing diagram and is feasible to be applied to the SC circuits. The proposed programmable gain controller(PGC) circuit has the 80 level settings of the LOSS range from 0 dB to -79 dB by a step of -1 dB. It has the monotonically logarithmic increments with maximum deviation of -0.53 dB in the range of 0 dB to -59 dB and -0.83 dB in the range of 0 dB to -79 dB.
|Number of pages||8|
|State||Published - 1 Dec 1994|
|Event||Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan|
Duration: 5 Dec 1994 → 8 Dec 1994
|Conference||Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems|
|Period||5/12/94 → 8/12/94|