A set of new CMOS differential logic circuits are proposed for the true-single-phase clocking scheme in the pipelined systems. All the new logic circuits are insensitive to the clock slopes and free from race problem. Using the new logic circuits, the clock loading can be greatly reduced. They can be applied to high-packing-density and high-speed CMOS pipelined systems. An experimental chip has been fabricated and measured, which partly verifies the performance of the new logic circuits.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Dec 1994|
|Event||Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England|
Duration: 30 May 1994 → 2 Jun 1994