New CMOS differential logic circuits for true-single-phase pipelined systems

Hong Yi Huang*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

A set of new CMOS differential logic circuits are proposed for the true-single-phase clocking scheme in the pipelined systems. All the new logic circuits are insensitive to the clock slopes and free from race problem. Using the new logic circuits, the clock loading can be greatly reduced. They can be applied to high-packing-density and high-speed CMOS pipelined systems. An experimental chip has been fabricated and measured, which partly verifies the performance of the new logic circuits.

Original languageEnglish
Pages (from-to)15-18
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
DOIs
StatePublished - 1 Dec 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: 30 May 19942 Jun 1994

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