In this paper a new BiCMOS increased full swing inverter (IFSI) and a new BiCMOS increased full swing buffer (IFSB) for low voltage/low power ULSI (Ultra Large Scale Integration) systems are proposed. These circuits can operate at low internal voltage (Vint) and have low input signal swing. As long as Vint>|Vt| (assuming Vtn = -Vtp), the circuits can work properly. The proposed BiCMOS IFSC circuits are suitable for high-speed operations. When the capacitor load is larger than 0.6 pf, the propagation delay and the delay power product at different internal voltages are better than previous circuits under the same circuit design parameters. We also establish the relationship between the Kr = Kn/Kp ratio and the circuit area. This can avoid the trial and error step in the circuit sizing operation to reduce the power consumption.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong|
Duration: 9 Jun 1997 → 12 Jun 1997