A sizing and constrained optimization algorithm for CMOS (complementary metal-oxide semiconductor) combinational logic circuits is presented. A constrained optimization problem is first transformed to a Lagrange multiplier form with a suitable cost function. Various techniques are applied to choose optimization variables, initial guess, and optimization direction and to reduce the occurrence of local minimum. As an example, the algorithm is applied to the minimization of power dissipation with a fixed delay constraint for the sizing of CMOS (complementary metal-oxide semiconductor) combinational logic circuits. It is shown that due to the proper choice of optimization variables, initial guess values, and optimization directions and the reduced occurrence of local minimum in the algorithm, the efficiency of the sizing and optimization are improved. The algorithm can be applied to many other circuit optimization problems with constraints.
|Number of pages||5|
|State||Published - 1 Dec 1989|
|Event||International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan|
Duration: 17 May 1989 → 19 May 1989
|Conference||International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers|
|Period||17/05/89 → 19/05/89|