Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs

Ta-Hui Wang, C. W. Tsai, M. C. Chen, C. T. Chan, H. K. Chiang, S. Huang Lu, H. C. Hu, T. F. Chen, C. K. Yang, M. T. Lee, D. Y. Wu, J. K. Chen, S. C. Chien, S. W. Sun

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4nm) pMOS is observed. This result is believed due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.

Original languageEnglish
Title of host publication2003 IEEE International Reliability Physics Symposium Proceedings, IRPS 2003 - 41st Annual
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages437-441
Number of pages5
ISBN (Electronic)0780376498
DOIs
StatePublished - 21 Jul 2003
Event2003 41st Annual IEEE International Reliability Physics Symposium, IRPS 2003 - Dallas, United States
Duration: 30 Mar 20034 Apr 2003

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2003-January
ISSN (Print)1541-7026

Conference

Conference2003 41st Annual IEEE International Reliability Physics Symposium, IRPS 2003
CountryUnited States
CityDallas
Period30/03/034/04/03

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