Negative capacitance enables FinFET and FDSOI scaling to 2 nm node

Vita Pi Ho Hu, Pin Chieh Chiu, Angada B. Sachid, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm. According to ITRS 2.0, FinFET scaling ends at 6/5nm node due to the scaling limits of fin width (6 nm Wfin) and FDSOI scaling ends at 11/10 nm due to scaling limit of the channel thickness (3 nm Tch). We present TCAD simulation evidence that using these Wfin and Tch, and negative capacitance enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100nA/μm and 10%∼29% higher Ion compared with 2nm FinFET(97μA/μm Ioff) and FDSOI(46μA/μm Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI.

Original languageEnglish
Title of host publication2017 IEEE International Electron Devices Meeting, IEDM 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages23.1.1-23.1.4
ISBN (Electronic)9781538635599
DOIs
StatePublished - 23 Jan 2018
Event63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States
Duration: 2 Dec 20176 Dec 2017

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference63rd IEEE International Electron Devices Meeting, IEDM 2017
CountryUnited States
CitySan Francisco
Period2/12/176/12/17

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