Nearly defect-free Ge gate-all-around FETs on Si substrates

Shu Han Hsu*, Chun Lin Chu, Wen Hsien Tu, Yen Chun Fu, Po Jung Sung, Hung Chih Chang, Yen Ting Chen, Li Yaw Cho, William Hsu, Guang Li Luo, C. W. Liu, Chen-Ming Hu, Fu Liang Yang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W fin) of 52nm and L g of 183nm has I on/I off =10 5, SS= 130mV/dec, and I on=235 μA/μm at -1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D it=2×10 12 cm -2eV -1 is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W eff) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing.

Original languageEnglish
Title of host publication2011 International Electron Devices Meeting, IEDM 2011
DOIs
StatePublished - 1 Dec 2011
Event2011 IEEE International Electron Devices Meeting, IEDM 2011 - Washington, DC, United States
Duration: 5 Dec 20117 Dec 2011

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2011 IEEE International Electron Devices Meeting, IEDM 2011
CountryUnited States
CityWashington, DC
Period5/12/117/12/11

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