Negative capacitance field-effect transistors (NCFETs) boost the electric field at the semiconductor-channel interface by virtue of the gate voltage amplification effect of a ferroelectric (fe) layer. NCFETs should be designed in such a way that this elevated field does not exceed the maximum electric field (Emax) determined by the reliability limit of the interfacial dielectric or NBTI/PBTI reliability. In this letter, a compact model-based methodology is presented to determine the NCFET design space considering several variables of the fe-layer and the baseline transistor, including the fe-layer thickness (Tfe), coercive field (Ec), remnant polarization (Pr), baseline transistor equivalent oxide thickness, supply voltage (Vdd), threshold voltage (Vth), and Emax. Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better ION/IOFF ratio and sub-threshold swing while operating at lower Vdd.
- sub 60mV/decade