A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and CDM ESD level of NAN SCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.
|Number of pages||6|
|Journal||IEEE International Reliability Physics Symposium Proceedings|
|State||Published - 1 Jan 2004|
|Event||42nd Annual IEEE International Reliability Physics Symposium, IRPS 2004 - Phoenix, United States|
Duration: 25 Apr 2004 → 29 Apr 2004
- ESD protection circuit