Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μ/m CMOS integrated circuits

Ming-Dou Ker, Kuo Chun Hsu

Research output: Contribution to journalConference articlepeer-review

9 Scopus citations


A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and CDM ESD level of NAN SCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.

Original languageEnglish
Article number1315356
Pages (from-to)381-386
Number of pages6
JournalIEEE International Reliability Physics Symposium Proceedings
Issue numberJanuary
StatePublished - 1 Jan 2004
Event42nd Annual IEEE International Reliability Physics Symposium, IRPS 2004 - Phoenix, United States
Duration: 25 Apr 200429 Apr 2004


  • CDM
  • ESD
  • ESD protection circuit
  • HBM
  • Latchup
  • SCR

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