Nanowire FET with Corner Spacer for High-Performance, Energy-Efficient Applications

Angada B. Sachid*, Hsiang Yun Lin, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

10 Scopus citations


Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total device capacitance which degrades device and circuit performance. This problem is exacerbated with the introduction of multigate FETs such as FinFET and gate-all-around FETs. In this paper, we introduce the corner spacer design for gate-all-around nanowire FET to significantly decrease parasitic capacitance with negligible degradation in ON-current. We show that the parasitic capacitance of a well-engineered corner spacer in a nanowire FET can be reduced by over 80% compared to the device with full nitride spacers. Ring oscillator stage delay and energy consumption of the corner spacer design are lower than the full spacer by over 50% each. This paper shows the possibility of engineering the spacers as a performance booster to continue scaling.

Original languageEnglish
Article number8089814
Pages (from-to)5181-5187
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number12
StatePublished - 1 Dec 2017


  • Corner spacer
  • nanowire FET
  • parasitic capacitance

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