Nanoscale multigate TiN metal nanocrystal memory using high-k blocking dielectric and high-work-function gate electrode integrated on silcon-on-insulator substrate

Chi Pei Lu*, Cheng Kei Luo, Bing-Yue Tsui, Cha Hsin Lin, Pei Jer Tzeng, Ching Chiun Wang, Ming Jinn Tsai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al 2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Original languageEnglish
Article number04C059
JournalJapanese journal of applied physics
Volume48
Issue number4 PART 2
DOIs
StatePublished - 1 Apr 2009

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