Abstract
A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices.
Original language | English |
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Pages (from-to) | 25-27 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 23 |
Issue number | 1 |
DOIs | |
State | Published - 1 Jan 2002 |
Keywords
- Chemical mechanical polishing (CMP)
- Critical dimension (CD)
- Double-gate
- FinFET
- Gate planarization
- Nanoscale CMOS
- Silicon-on-insulator (SOI)
- Spacer etch
- Spacer lithography
- Thin-body
- Uniformity