Nanoscale CMOS spacer FinFET for the terabit era

Yang Kyu Choi*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

151 Scopus citations

Abstract

A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices.

Original languageEnglish
Pages (from-to)25-27
Number of pages3
JournalIEEE Electron Device Letters
Volume23
Issue number1
DOIs
StatePublished - 1 Jan 2002

Keywords

  • Chemical mechanical polishing (CMP)
  • Critical dimension (CD)
  • Double-gate
  • FinFET
  • Gate planarization
  • Nanoscale CMOS
  • Silicon-on-insulator (SOI)
  • Spacer etch
  • Spacer lithography
  • Thin-body
  • Uniformity

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