Low temperature effects in the scaling of complementary metal oxide semiconductor (CMOS) integrated circuits were discussed. Experimental results showed that the temperature reduction enhanced the carrier mobility and helped in achieving ballistic transport. In circuits, it resulted in lower interconnect resistance and enabled latchup-free operations due to reduced bipolar gains.
|Number of pages||3|
|Journal||International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|State||Published - 1 Jan 2001|