Nanoscale CMOS at low temperature: Design, reliability, and scaling trend

Bin Yu, Haihong Wang, Concetta Riccobene, Hyeon Seag Kim, Qi Xiang, Ming Ren Lin, Leland Chang, Chen-Ming Hu

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

Low temperature effects in the scaling of complementary metal oxide semiconductor (CMOS) integrated circuits were discussed. Experimental results showed that the temperature reduction enhanced the carrier mobility and helped in achieving ballistic transport. In circuits, it resulted in lower interconnect resistance and enabled latchup-free operations due to reduced bipolar gains.

Original languageEnglish
Pages (from-to)23-25
Number of pages3
JournalInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs
StatePublished - 1 Jan 2001

Fingerprint Dive into the research topics of 'Nanoscale CMOS at low temperature: Design, reliability, and scaling trend'. Together they form a unique fingerprint.

  • Cite this