Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON

C. J. Su, Y. T. Tang, Y. C. Tsou, P. J. Sung, F. J. Hou, C. J. Wang, S. T. Chung, C. Y. Hsieh, Y. S. Yeh, F. K. Hsueh, K. H. Kao, S. S. Chuang, C. T. Wu, T. Y. You, Y. L. Jian, T. H. Chou, Y. L. Shen, B. Y. Chen, G. L. Luo, T. C. HongK. P. Huang, M. C. Chen, Y. J. Lee, Tien-Sheng Chao, Tseung-Yuen Tseng, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Y. H. Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO x (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al 2 O 3 IL results in paraelectric behavior, HZO on GeO x IL exhibits significant FE. High I on /I off (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L g ) of 60 nm and a FE-HZO/GeO x gate stack.

Original languageEnglish
Title of host publication2017 Symposium on VLSI Technology, VLSI Technology 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT152-T153
ISBN (Electronic)9784863486058
DOIs
StatePublished - 31 Jul 2017
Event37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, Japan
Duration: 5 Jun 20178 Jun 2017

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference37th Symposium on VLSI Technology, VLSI Technology 2017
CountryJapan
CityKyoto
Period5/06/178/06/17

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