Nano-meter scaled gate area high-K dielectrics with trap-assisted tunneling and random telegraph noise

Po Jui Jerry Lin*, Zhe An Andy Lee, Chih Wei Kira Yao, Hsin Jyun Vincent Lin, Watanabe Hiroshi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

If the trap density is 1012 cm-2, then there are only one trap in 10nm × 10nm on average. Accordingly, three-dimensional simulation that is sensitive to the movement of sole electron is indispensable for carefully investigating the reliability issues related to local traps in future nano-electron devices. As a demonstration, we investigate Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT) at the same moment in 5nm×5nm gate area high-K dielectrics (EOT= 0.8nm to 0.47nm). The simulation is carried out with respect to various gate biases, physical thickness of high-K, interlayer suboxide thickness, and dielectric constant of high-K. It is suggested that thinner suboxide and higher permittivity can suppress the increase of the leakage current which is caused by TAT.

Original languageEnglish
Title of host publicationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages241-244
Number of pages4
ISBN (Electronic)9781479952885
DOIs
StatePublished - 20 Oct 2014
Event2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014 - Yokohama, Japan
Duration: 9 Sep 201411 Sep 2014

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014
CountryJapan
CityYokohama
Period9/09/1411/09/14

Keywords

  • high-K dielectrics
  • interlayer suboxide
  • random telegraph noise
  • simulation
  • single-electron
  • trap-assisted tunneling

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    Lin, P. J. J., Lee, Z. A. A., Yao, C. W. K., Lin, H. J. V., & Hiroshi, W. (2014). Nano-meter scaled gate area high-K dielectrics with trap-assisted tunneling and random telegraph noise. In International Conference on Simulation of Semiconductor Processes and Devices, SISPAD (pp. 241-244). [6931608] (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2014.6931608