Multithreaded coprocessor interface for multi-core multimedia SoC

Shih H. Ou; Tay J. Lin; Xiang Sheng Deng; Zhi Hong Zhuo; Chih-Wei Liu

doi:10.1109/ASPDAC.2008.4483922

Multithreaded coprocessor interface for multi-core multimedia SoC

Shih H. Ou^*, Tay J. Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.

Original language	English
Title of host publication	2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages	115-116
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2008.4483922
State	Published - 21 Aug 2008
Event	2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of Duration: 21 Mar 2008 → 24 Mar 2008

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Country	Korea, Republic of
City	Seoul
Period	21/03/08 → 24/03/08

Access to Document

10.1109/ASPDAC.2008.4483922

Link to publication in Scopus

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Cite this

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title = "Multithreaded coprocessor interface for multi-core multimedia SoC",

abstract = "Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.",

author = "Ou, {Shih H.} and Lin, {Tay J.} and Deng, {Xiang Sheng} and Zhuo, {Zhi Hong} and Chih-Wei Liu",

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doi = "10.1109/ASPDAC.2008.4483922",

language = "English",

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series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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Ou, SH, Lin, TJ, Deng, XS, Zhuo, ZH & Liu, C-W 2008, Multithreaded coprocessor interface for multi-core multimedia SoC. in 2008 Asia and South Pacific Design Automation Conference, ASP-DAC., 4483922, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 115-116, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, Seoul, Korea, Republic of, 21/03/08. https://doi.org/10.1109/ASPDAC.2008.4483922

Multithreaded coprocessor interface for multi-core multimedia SoC. / Ou, Shih H.; Lin, Tay J.; Deng, Xiang Sheng; Zhuo, Zhi Hong; Liu, Chih-Wei.

2008 Asia and South Pacific Design Automation Conference, ASP-DAC. 2008. p. 115-116 4483922 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.

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