Multiplierless multirate decimator / interpolator module generator

Shyh-Jye Jou*, Kai Yuan Jheng, Hsiao Yun Chen, An Yeu Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

A module generator, which can automate the process of designing high-speed low-complexity multistage multirate decimator / interpolator, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. A filter design example with TSMC 0.25μm standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity applications. Moreover, for high-speed application, the chip can operate at 714MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Pages58-61
Number of pages4
DOIs
StatePublished - 1 Dec 2004
EventProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
Duration: 4 Aug 20045 Aug 2004

Publication series

NameProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference

ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
CountryJapan
CityFukuoka
Period4/08/045/08/04

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