Multiplier architecture power consumption characterization for low-power DSP applications

Sangjin Hong*, Shu Shin Chin, Suhwan Kim, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper presents a multiplier power consumption characterization technique used in a coefficient optimization for low-power multimedia digital signal processing. The technique accurately characterizes and models the actual power consumption of the multipliers. Based on the models, the coefficient optimization finds an optimum set of coefficient patterns. The technique is based on the relative power weight factor of each coefficient bit is defined which characterizes the power consumption of multipliers. We have developed power consumption models based on the relative power weight factors to estimate/predict power dissipation for array-type multipliers and tree-type multipliers. We have applied our methodology on FFT for obtaining the profiles of power consumption for these multiplier structures.

Original languageEnglish
Title of host publicationICECS 2002 - 9th IEEE International Conference on Electronics, Circuits and Systems
Pages741-744
Number of pages4
DOIs
StatePublished - 1 Dec 2002
Event9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002 - Dubrovnik, Croatia
Duration: 15 Sep 200218 Sep 2002

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume2

Conference

Conference9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002
CountryCroatia
CityDubrovnik
Period15/09/0218/09/02

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  • Cite this

    Hong, S., Chin, S. S., Kim, S., & Hwang, W. (2002). Multiplier architecture power consumption characterization for low-power DSP applications. In ICECS 2002 - 9th IEEE International Conference on Electronics, Circuits and Systems (pp. 741-744). [1046275] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2). https://doi.org/10.1109/ICECS.2002.1046275