Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area

Ming-Dou Ker*, Chung-Yu Wu, Chien Chang Huang, Tung Yang Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

A new multiple-cell square-type layout design is proposed to realize the large-dimension output transistors for submicron low-voltage CMOS ICs. By using this layout design, the layout area of CMOS output buffers can be effectively reduced 30-40% with respect to the traditional finger-type layout. The drain-to-bulk parasitic capacitance of the output transistors is also reduced 40% by this square-type layout. Experimental results in a 0.6 μm CMOS process have shown that the maximum driving (sinking) capability per unit layout area of a CMOS output buffer realized by the proposed multiple-cell square-type layout is improved 54% (34%) more than that by the traditional finger-type layout. The human-body-model (machine-model) ESD robustness per unit layout area of the CMOS output buffer realized by the proposed multiple-cell square-type layout is increased 25.2% (17.3%) as comparing to that by the traditional finger-type layout.

Original languageEnglish
Pages (from-to)1007-1014
Number of pages8
JournalSolid-State Electronics
Volume42
Issue number6
DOIs
StatePublished - 1 Jan 1998

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