A multichip module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's 'faster, better, cheaper' missions. The MCM based processor incorporates a complete 32-bit RISC computer including RAM, EEPROM and programmable hardware. This paper describes the system architecture and its associated MCM design and implementation. It also explores the architectural merits of including user programmable hardware.
|Number of pages||4|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|State||Published - 1 Dec 1995|
|Event||Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA|
Duration: 18 Sep 1995 → 22 Sep 1995