Multiband RF-interconnect for reconfigurable network-on-chip communications

Jason Cong*, Mau-Chung Chang, Glenn Reinman, Sai Wang Tam

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

One of the key benefits of the scaling of CMOS is that the switching speed of the transistor improves over each technology generation. According to ITRS, fT and fmax, will be 600GHz and 1 THz, respectively, in 16nm CMOS technology. With the advance in CMOS mm-wave circuits, hundreds of GHz bandwidth will be available in the near future. In addition, compared with CMOS repeaters charging and discharging the wire, EM waves travel in a guided medium at the speed of light which is about 10ps/mm on silicon substrate. The question here is: How can we utilize over hundreds of GHz of bandwidth in a future mobile system through RF-I while concurrently achieving ultra-low power operation and dynamic allocation in bandwidth to meet future Network-on-Chip needs?

Original languageEnglish
Title of host publicationSLIP'09 - Proceedings of the 2009 ACM/IEEE Workshop on System Level Interconnect Prediction
Pages107-108
Number of pages2
DOIs
StatePublished - 1 Dec 2009
Event2009 ACM/IEEE Workshop on System Level Interconnect Prediction, SLIP'09 - San Francisco, CA, United States
Duration: 26 Jul 200927 Jul 2009

Publication series

NameInternational Workshop on System Level Interconnect Prediction, SLIP

Conference

Conference2009 ACM/IEEE Workshop on System Level Interconnect Prediction, SLIP'09
CountryUnited States
CitySan Francisco, CA
Period26/07/0927/07/09

Keywords

  • Chip multiprocessor
  • FDMA
  • MORFIC
  • Network-on-chip
  • Reconfigurable
  • RF-interconnect

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