Multi-gigabit serial link transmitter- Off-chip and on-chip

Shyh-Jye Jou*, Chih Hsien Lin, Chih Ning Chen, You Jiun Wang, Ju Yuan Hsiao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multi-Gbps serial link transmitter for both off-chip and on-chip transmission are presented. For off-chip transmission, a new pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented using tsmc 0.18 um CMOS process. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results. For on-chip transmission, SerDes based serial link architecture is used in on-chip application. Using tsmc 0.13 um CMOS process, the operation speed and power consumption are 5 Gbps and 3.2 mW respectively with the interconnect area is half of parallel architecture.

Original languageEnglish
Title of host publicationEmerging Information Technology Conference 2005
Pages137-140
Number of pages4
DOIs
StatePublished - 1 Dec 2005
EventEmerging Information Technology Conference 2005 - Taipei, Taiwan
Duration: 15 Aug 200516 Aug 2005

Publication series

NameEmerging Information Technology Conference 2005
Volume2005

Conference

ConferenceEmerging Information Technology Conference 2005
CountryTaiwan
CityTaipei
Period15/08/0516/08/05

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    Jou, S-J., Lin, C. H., Chen, C. N., Wang, Y. J., & Hsiao, J. Y. (2005). Multi-gigabit serial link transmitter- Off-chip and on-chip. In Emerging Information Technology Conference 2005 (pp. 137-140). [1544368] (Emerging Information Technology Conference 2005; Vol. 2005). https://doi.org/10.1109/EITC.2005.1544368