Multi-gigabit pre-emphasis design and analysis for serial link

Chih Hsien Lin*, Chang Hsiao Tsai, Chih Ning Chen, Shyh-Jye Jou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18 μm 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results.

Original languageEnglish
Pages (from-to)2009-2019
Number of pages11
JournalIEICE Transactions on Electronics
VolumeE88-C
Issue number10
DOIs
StatePublished - 1 Jan 2005

Keywords

  • Coaxial cable
  • High-speed serial link
  • Pre-emphasis
  • Transmitter

Fingerprint Dive into the research topics of 'Multi-gigabit pre-emphasis design and analysis for serial link'. Together they form a unique fingerprint.

Cite this