Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor

Alan P. Su; Jiff Kuo; Kuen Jong Lee; Ing Jer Huang; Guo An Jian; Cheng An Chien; Jiun-In  Guo; Chien Hung Chen

doi:10.1109/VDAT.2011.5783594

Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor

Alan P. Su, Jiff Kuo, Kuen Jong Lee, Ing Jer Huang, Guo An Jian, Cheng An Chien, Jiun-In Guo, Chien Hung Chen

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find comprehensive multi-core software/hardware co-debug capability that can stop at not only software but also hardware breakpoints to inspect data and system status for identifying bugs. In this work we have integrated various debug mechanisms so that the entire multi-core SoC is able to iterate unlimited times of software and hardware breaks for data and status inspections and stepping forward to resume execution till next break point. This debug mechanism is realized with a chip with four ARM1176 cores and ARM CoreSight™ on-chip debug and trace system, a Field Programmable Gate Array (FPGA) loaded with on-chip test architecture and bus monitor, and software debug platform to download system trace and processor core data for inspection and debug control. Key contributions of this work are (1) a development of multi-clock multi-core software/hardware co-debug platform and (2) the exercise of a multi-core program debugging to visualize the physical behavior of race conditions.

Original language	English
Title of host publication	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages	129-134
Number of pages	6
DOIs	https://doi.org/10.1109/VDAT.2011.5783594
State	Published - 28 Jun 2011
Event	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan Duration: 25 Apr 2011 → 28 Apr 2011

Publication series

Name	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Country	Taiwan
City	Hsinchu
Period	25/04/11 → 28/04/11

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Su, A. P., Kuo, J., Lee, K. J., Huang, I. J., Jian, G. A., Chien, C. A., Guo, J-I., & Chen, C. H. (2011). Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (pp. 129-134). [5783594] (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). https://doi.org/10.1109/VDAT.2011.5783594

Su, Alan P. ; Kuo, Jiff ; Lee, Kuen Jong ; Huang, Ing Jer ; Jian, Guo An ; Chien, Cheng An ; Guo, Jiun-In ; Chen, Chien Hung. / Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor. Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. pp. 129-134 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

@inproceedings{2fe5f9e1f8b44eac88898d005525874b,

title = "Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor",

abstract = "Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find comprehensive multi-core software/hardware co-debug capability that can stop at not only software but also hardware breakpoints to inspect data and system status for identifying bugs. In this work we have integrated various debug mechanisms so that the entire multi-core SoC is able to iterate unlimited times of software and hardware breaks for data and status inspections and stepping forward to resume execution till next break point. This debug mechanism is realized with a chip with four ARM1176 cores and ARM CoreSight{\texttrademark} on-chip debug and trace system, a Field Programmable Gate Array (FPGA) loaded with on-chip test architecture and bus monitor, and software debug platform to download system trace and processor core data for inspection and debug control. Key contributions of this work are (1) a development of multi-clock multi-core software/hardware co-debug platform and (2) the exercise of a multi-core program debugging to visualize the physical behavior of race conditions.",

author = "Su, {Alan P.} and Jiff Kuo and Lee, {Kuen Jong} and Huang, {Ing Jer} and Jian, {Guo An} and Chien, {Cheng An} and Jiun-In Guo and Chen, {Chien Hung}",

year = "2011",

month = jun,

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doi = "10.1109/VDAT.2011.5783594",

language = "English",

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series = "Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011",

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note = "null ; Conference date: 25-04-2011 Through 28-04-2011",

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Su, AP, Kuo, J, Lee, KJ, Huang, IJ, Jian, GA, Chien, CA, Guo, J-I & Chen, CH 2011, Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783594, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, pp. 129-134, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, Taiwan, 25/04/11. https://doi.org/10.1109/VDAT.2011.5783594

Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor. / Su, Alan P.; Kuo, Jiff; Lee, Kuen Jong; Huang, Ing Jer; Jian, Guo An; Chien, Cheng An; Guo, Jiun-In ; Chen, Chien Hung.

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 129-134 5783594 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Su AP, Kuo J, Lee KJ, Huang IJ, Jian GA, Chien CA et al. Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 129-134. 5783594. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). https://doi.org/10.1109/VDAT.2011.5783594

Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor

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