Shyh-Jye Jou*, Chein Wei Jen, Wen Zen Shen, Chung Len Lee

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review


An MOS timing simulator, MOTA, is presented. Similar to MOTIS and MOTIS-C, MOTA employs the node-decoupling, one sweep Gauss-Seidel and table model techniques to improve simulation speed. The simulator has three distinct features: (1) it provides a subcircuit allowing a user to simulate tightly coupled circuits to obtain the necessary accuracy; (2) it employs a physical table model for MOS transistors with only 240 storage points while still giving a good accuracy; (3) it employs a bypass time step control scheme to increase the simulation speed. It has been implemented in C on a VAX-11/780 and shown to be approximately two orders faster than SPICE-2G. 5.

Original languageEnglish
Number of pages2
StatePublished - 1 Dec 1984

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