MOSFET scaling into the 10 nm regime

Leland Chang, Chen-Ming Hu

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

Scaling limits of the double-gate MOSFET structure are explored. Because short-channel effects can be adequately controlled by thinning the silicon body, the eventual scaling limit will be determined by the ability to control off-state leakage due to quantum mechanical tunneling and thermionic emission between the source and drain. Depending on threshold voltage and the source/drain doping profile, this will restrict gate length scaling to 5-11 nm. As power supplies are scaled down, maintaining on-state drive current may become difficult due to threshold voltage limitations. Series resistance becomes important as the body thickness is reduced, but intrinsic device performance may still be improved.

Original languageEnglish
Pages (from-to)351-355
Number of pages5
JournalSuperlattices and Microstructures
Volume28
Issue number5-6
DOIs
StatePublished - 1 Jan 2000

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