This article describes a conceptual framework for understanding MOSFET scaling by establishing the goals and constraints of scaling. It concludes that judicious shrinking of MOSFET device dimensions can sustain the historical trend of device size reduction through the 0.09 μm generation of technology, which may be used for IC production in the year 2007. Direct tunneling in gate oxides clouds the future beyond that. From 0.5 μm technology onward; logic gate speed will double every four generations rather than two, as in the past, unless technology innovations pick up the slack.
|State||Published - 1 Jun 1994|