Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS

E. McShane*, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi  Fang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A monolithic RFIC in 0.25-micron fully-depleted SOI CMOS has been designed consisting of a microcoded 8-bit 33-MHz microprocessor, a 400-MHz 8-bit ASK-modulated RF transceiver, and two integrated dc-dc voltage converters for power management. This architecture exploits a low-power (sub 2-V) digital process for mixed-signal VLSI in a die size measuring 2.2 mm × 2.2 mm.

Original languageEnglish
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages332-333
Number of pages2
ISBN (Print)0769501044
DOIs
StatePublished - 1 Dec 1999
EventProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Duration: 4 Mar 19996 Mar 1999

Publication series

NameProceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)1066-1395

Conference

ConferenceProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
CityAnn Arbor, MI, USA
Period4/03/996/03/99

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    McShane, E., Shenai, K., Alkalai, L., Kolawa, E., Boyadzhyan, V., Blaes, B., & Fang, W-C. (1999). Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 332-333). (Proceedings of the IEEE Great Lakes Symposium on VLSI). IEEE. https://doi.org/10.1109/GLSV.1999.757446